Conventional PCI (PCI is an initialism formed from Peripheral Component Interconnect, part of the PCI Local Bus standard and often shortened to PCI) is a computer bus for attaching hardware devices in a computer.These devices can take either the form of an integrated circuit fitted onto the motherboard itself, called a planar device in the PCI specification, or an expansion card that fits into a slot.The PCI Local Bus was first implemented in IBM PC compatibles, where it displaced the combination of ISA plus one VESA Local Bus as the bus configuration.PCI is being replaced by PCI-X and PCI Express, but as of 2011, most motherboards are still made with one or more PCI slots, which are sufficient for many uses.
Typical PCI cards used in PCs include: network cards, sound cards, modems, extra ports such as USB or serial, TV tuner cards and disk controllers.
PCI video cards replaced ISA and VESA cards, until growing bandwidth requirements outgrew the capabilities of PCI; the preferred interface for video cards became AGP, and then PCI Express.
PCI video cards remain available for use with old PCs without AGP or PCI Express slots.
Many devices previously provided on PCI expansion cards are now commonly integrated onto motherboards or available in universal serial bus and PCI Express versions.
In mainstream PCs, PCI was slower to replace VESA Local Bus (VLB), and did not gain significant market penetration until late 1994 in second-generation Pentium PCs.
Apple Computer adopted PCI for professional Power Macintosh computers (replacing NuBus) in mid-1995, and the consumer Performa product line (replacing LC PDS) in mid-1996.
Since then, motherboard manufacturers have included progressively fewer Conventional PCI slots in favor of the new standard.
A third address space, called the PCI Configuration Space, which uses a fixed addressing scheme, allows software to determine the amount of memory and I/O address space needed by each device.
In a typical system, the firmware (or operating system) queries all PCI buses at startup time (via PCI Configuration Space) to find out what devices are present and what system resources (memory space, I/O space, interrupt lines, etc.) each needs.
The PCI configuration space also contains a small amount of device type information, which helps an operating system choose device drivers for it, or at least to have a dialogue with a user about the system configuration.
These are typically necessary for devices used during system startup, before device drivers are loaded by the operating system.
In addition there are PCI Latency Timers that are a mechanism for PCI Bus-Mastering devices to share the PCI bus fairly.
"Fair" in this case means that devices won't use such a large portion of the available PCI bus bandwidth that other devices aren't able to get needed work done.
The PCI bus includes four interrupt lines, all of which are available to each device.
Single-function devices use their INTA# for interrupt signaling, so the device load is spread fairly evenly across the four available interrupt lines.
PCI bridges (between two PCI buses) map the four interrupt traces on each of their sides in varying ways.
The mapping of PCI interrupt lines onto system interrupt lines, through the PCI host bridge, is similarly implementation-dependent.
PCI Express does not have physical interrupt lines at all.
The PCI specification also provides options for 3.3 V signaling, 64-bit bus width, and 66 MHz clocking, but these are not commonly encountered outside of PCI-X support on server motherboards.
Typical PCI cards have either one or two key notches, depending on their signaling voltage.
Mini PCI was added to PCI version 2.2 for use in laptops; it uses a 32-bit, 33 MHz bus with powered connections (3.3 V only; 5 V is limited to 100 mA) and support for bus mastering and DMA.
The standard size for Mini PCI cards is approximately a quarter of their full-sized counterparts.
As there is no access to the card from outside the case, unlike desktop PCI cards with brackets carrying connectors, there are limitations on the functions they may perform.
Many Mini PCI devices were developed such as Wi-Fi, Fast Ethernet, Bluetooth, modems (often Winmodems), sound cards, cryptographic accelerators, SCSI, IDE–ATA, SATA controllers and combination cards.
Mini PCI cards can be used with regular PCI-equipped hardware, using Mini PCI-to-PCI converters.
Mini PCI has been superseded by the much narrower PCI Express Mini Card.
Mini PCI cards have a 2 W maximum power consumption, which limits the functionality that can be implemented in this form factor.
In some small-form-factor systems, this may not be sufficient to allow even "half-length" PCI cards to fit.
Despite this limitation, these systems are still useful because many modern PCI cards are considerably smaller than half-length.
PCI bus traffic consists of a series of PCI bus transactions.
The direction of the data phases may be from initiator to target (write transaction) or vice-versa (read transaction), but all of the data phases must be in the same direction.
(One common example is a low-performance PCI device that does not support burst transactions, and always halts a transaction after the first data phase.)
To ensure compatibility with 32-bit PCI devices, it is forbidden to use a dual address cycle if not necessary, i.e. if the high-order address bits are all zero.
While the PCI bus transfers 32 bits per data phase, the initiator transmits a 4 byte enable signals indicating which 8-bit bytes are to be considered significant.
PCI has three address spaces: memory, I/O address, and configuration.
Although the PCI bus specification allows burst transactions in any address space, most devices only support it for memory addresses and not I/O.
Finally, PCI configuration space provides access to 256 bytes of special configuration registers per PCI device.
The registers are used to configure devices memory and I/O address ranges they should respond to from transaction initiators.
If an address is not claimed by any device, the transaction initiator's address phase will time out causing the initiator to abort the operation.
With the exception of the unique dual address cycle, the least significant bit of the command code indicates whether the following data phases are a read (data sent from target to initiator) or a write (data sent from an initiator to target).
Soon after promulgation of the PCI specification, it was discovered that lengthy transactions by some devices, due to slow acknowledgments, long data bursts, or some combination, could cause buffer underrun or overrun in other devices.
In a delayed transaction, the target records the transaction (including the write data) internally and aborts (asserts STOP# rather than TRDY#) the first data phase.
